Bus Architecture

A computer bus acts as pathway for information between various components. Technological changes have produced various bus architectures as manufacturers seek to address consumer demands. Common bus architectures include Industry Standard Architecture (ISA), Micro Channel Architecture (MCA), Video Electronics Standards Association (VESA), Extended Industry Standard Architecture (EISA), Peripheral Component Interconnect (PCI) and Accelerate Graphics Port (AGP).

The ISA bus originally used an 8-bit design for data transfer. It operated at an estimated clock speed of 4.77 MHZ. Improvements in the bus design have led to the development of a 16-bit bus, which supports 24 address lines. The AT bus operates at a clock speed of 8MHZ.  The MCA bus was an improvement of the ISA bus. This bus supports both 16-bit and 32-bit data operations. Furthermore, it has an enhanced clock speed of 10 MHZ. It also supports bus mastering which enhances CPU performance. EISA bus architecture supports 32-bit data operations and 32 address lines that enhance memory access up to about 4 GB (Comer, 2005). It operates at a clock speed of 8 MHZ in order to cater for compatibility with ISA. The design of VESA bus largely focused on the standardization of video specifications. This bus supports 32-bit data operations and operates a high clock speed of either 25 or 33 MHZ. VESA design required the bus to operate at near the clock speeds of CPUs. Compatibility issues arose as CPUs speed increased. The PCI bus supports 32-bit and 64-bit data operations. The data width of the bus is the same as that of the host processor CPU (Hennessy & Patterson, 1998). This bus operates at a clock speed of 33 MHZ. Furthermore, it supports the bus mastering technology. The design of the AGP bus focused on the enhancement of computer video performance. It operates at speeds equal to that of the host CPU bus. This bus supports high data transfer rates ranging from 264 Mbps to 1.5 Gbps (Stallings, 2000).